In multiprocessor systems, data transfer between processors may be necessary in the course of a process. In a multiprocessor system including a shared cache memory, it is considered to perform data transfer through the shared cache memory used as a shared FIFO. As a control technique for the shared cache memory in related art, the MESI protocol having four states, i.e., M (Modified), E (Exclusive), S (Shared), and I (Invalid) is known. More specifically, a need for a write-back to a main memory is allowed to be determined by controlling each cache line to be marked with one of the four states. As related art of this kind, for example, an inclusive shared cache among multiple core-cache clusters with use of the MESI protocol is proposed (for example, refer to PTL 1).